Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable system on a chips (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, a multi-step process is used to implement the user design in the PLD. In some cases, this process includes the steps of synthesis, mapping, placement, and routing. These steps can consume extensive processing resources—especially the mapping, placement, and routing steps which collectively determine the physical implementation of the user design in the PLD.
Because the user design becomes highly optimized for the PLD through this process, subsequent changes to the user design (e.g., enhancements, improvements, or corrections) can significantly impact the final implementation of the user design in the PLD. Thus, if changes to the user design are required, conventional processes require most or all of the process steps to be repeated (e.g., rerun) which can incur significant processing time and resources. Unfortunately, as PLD sizes continue to grow, this processing is compounded.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.